The present invention relates to a semiconductor design technology; more particularly, to an on-die termination circuit capable of compensating for an error in resolution.
Generally, various semiconductor devices implemented by integrated circuits such as CPU, memories and gate arrays are used for various digital products such as personal computers, servers and work stations. For the most part, the semiconductor devices have a receiving circuit for receiving signals from external circuits through input pads and an output circuit for providing internal signals to the external circuits through output pads.
Meanwhile, as the operation speed of the digital products becomes higher, the swing of the signals which are interfaced between the semiconductor devices is decreased. The reason why the swing is getting smaller is that it is necessary to minimize the transmission time of the signals. However, the smaller the swing is, the more the semiconductor devices are influenced by external noise and the more the echo-back signal caused by impedance mismatching is serious at the interface. The impedance mismatching is generated by an external noise, a change of power supply voltage or temperature and a change of manufacturing process of the semiconductor devices. If the impedance mismatching is created, it is difficult to transmit the data at high speed and the data outputted from an output terminal of the semiconductor device can be distorted. Therefore, in the case that the semiconductor device at the receiving side receives the distorted output signal through its input terminal, the problems such as setup/hold failure or the misjudgment of an input signal level can be caused frequently.
Therefore, the semiconductor device at the receiving side, in which the high speed operation is required, employs an impedance matching circuit, which is called on-die termination, in the vicinity of a pad within the integrated circuit chip. Generally, as to the on-die termination scheme, a source termination is carried out at the transmitting side by the output circuit and a parallel termination is performed at the receiving side by a termination circuit which is in parallel coupled to a receiving circuit connected to the input pad.
FIG. 1 is a block diagram illustrating an on-die termination circuit of a conventional semiconductor memory device.
Referring to FIG. 1, the on-die termination circuit according to the conventional semiconductor memory device includes: an ODT control unit 30 for sequentially activating a plurality of control signals ODT_EN1P/N, ODT_EN2P/N and DT_UPP/N, in this order, in response to a driving signal RES; a first resistance feedback unit 20 to receive a pull-up code signal P_LEG_CD<0:4> and an input resistance ZQ for outputting a feedback pull-up resistance P_LEG_FD; a first termination resistance supply unit 10 for outputting a pull-up resistance P_LEG_RSS corresponding to the pull-up code signal P_LEG_CD<0:4>; a first code signal adjusting unit (including the reference numerals 40 and 50) for adjusting the pull-up code signal P_LEG_CD<0:4> in response to the plurality of control signals ODT_EN1P, ODT_EN2P and DT_UPP in order that the feedback pull-up resistance P_LEG_FD has a level corresponding to a reference resistance RSS_REF; a second resistance feedback unit 70 to receive a pull-down code signal N_LEG_CD<0:4> and the pull-up code signal P_LEG_CD<0:4> for outputting a feedback pull-down resistance N_LEG_FD; a second code signal adjusting unit (including the reference numerals 80 and 90) for adjusting the pull-down code signal N_LEG_CD<0:4> in response to a plurality of control signals ODT_EN1N, ODT_EN2N, DT_UPN in order that the feedback pull-down resistance N_LEG_FD has a level corresponding to the reference resistance RSS_REF; and a second termination resistance supply unit 60 for outputting a pull-down resistance N_LEG_RSS corresponding to the pull-down code signal N_LEG_CD<0:4>.
Here, the first code signal adjusting unit includes: a first level detecting unit 42 for detecting a level of the feedback pull-up resistance P_LEG_FD, based on the reference resistance RSS_REF, in response to the control signal ODT_EN1P and for outputting a pull-up detecting signal P_LEG_SN; a first amplifier 44 for amplifying the pull-up detecting signal P_LEG_SN in response to the control signal ODT_EN2P and for outputting a pull-up level signal P_LEG_DT; and a first register 50 for storing the pull-up level signal P_LEG_DT and outputting the pull-up code signal P_LEG_CD<0:4> in response to the control signal DT_UPP.
Similarly, the second code signal adjusting unit includes: a second level detecting unit 82 for detecting a level of the feedback pull-down resistance N_LEG_FD, based on the reference resistance RSS_REF, in response to the control signal ODT_EN1N and for outputting a pull-down detecting signal N_LEG_SN; a second amplifier 84 for amplifying the pull-down detecting signal N_LEG_SN in response to the control signal ODT_EN2N and for outputting a pull-down level signal P_LEG_DT; and a second register 90 for storing the pull-down level signal P_LEG_DT and outputting the pull-down code signal N_LEG_CD<0:4> in response to the control signal DT_UPN.
At the time of the activation of the driving signal RES, the ODT control unit 30 sequentially activates the control signals ODT_EN1P, ODT_EN2P and DT_UPP and then the control signals ODT_EN1N, ODT_EN2N and DT_UPN. Thereafter, this operation is repeated for a predetermined number of times under the control of the ODT control unit 30.
Even though it is not shown in FIG. 1, the pull-up resistance P_LEG_RSS and the pull-down resistance N_LEG_RSS are on-die termination resistances which are coupled to the corresponding data pads.
Also, the first level detecting unit 42 includes a current mirror type differential amplifier to which the feedback pull-up resistance P_LEG_FD and the reference resistance RSS_REF are applied and the second level detecting unit 82 also includes a current mirror type differential amplifier. The first and second amplifiers 44 and 84 respectively include a voltage cross-coupled amplifier. The first and second registers 50 and 90 respectively include a latch to latch the corresponding input signals P_LEG_DT and N_LEG_DT in response to the corresponding control signals DT_UPP/N.
FIG. 2 is a schematic circuit diagram illustrating the first resistance feedback unit 20 described in FIG. 1. Referring to FIG. 2, the first resistance feedback unit 20 includes first to fifth PMOS transistors, which are turned on in response to the corresponding pull-up code signal P_LEG CD<0:4>, and first to fifth resistors each of which is connected between a common output node and a respective PMOS transistor. The feedback pull-up resistance P_LEG_FD is a signal corresponding to the level of voltage applied to the common output node.
The first resistance feedback unit 20 receives the input resistance ZQ at its output node and the input resistance ZQ is applied from an external circuit through an input pin. The resistance of 240Ω is applied between the input pin and a ground voltage. Therefore, in the first resistance feedback unit 20, the number of transistors, which are turned on, is determined by the pull-up code signal P_LEG_CD<0:4>. The feedback pull-up resistance P_LEG_FD is determined by parallel resistance value of resistors which are in series connected to their respective turn-on PMOS transistors.
On the other hand, the first termination resistance supply unit 10, which has the same configuration as the first resistance feedback unit 20 shown in FIG. 2, supplies the pull-up resistance P_LEG_RSS.
FIG. 3 is a schematic circuit diagram illustrating the second resistance feedback unit 70 described in FIG. 1.
As shown in FIG. 3, the second resistance feedback unit 70 includes a first resistance unit 32, which is connected to an output node, in order to supply a first code resistance corresponding to the pull-up code signal P_LEG_CD<0:4> and a second resistance unit 34, which is connected to the output node, in order to supply a second code resistance corresponding to the pull-down code signal N_LEG_CD<0:4>. The feedback pull-down resistance N_LEG_FD is a signal corresponding to the level of voltage applied to the output node.
The first resistance unit 32 includes first to fifth PMOS transistors, which are turned on in response to the corresponding pull-up code signal P_LEG_CD<0:4>, and first to fifth resistors each of which is connected between a common output node and each PMOS transistor. The second resistance unit 34 includes first to fifth resistors, each of which is connected to the common output node, and first to fifth NMOS transistors, which are disposed between the resistors and the ground voltage VSSQ and respectively turned on in response to the corresponding pull-down code signal N_LEG_CD<0:4>.
That is, the second resistance feedback unit 70 supplies the feedback pull-down resistance N_LEG_FD which is determined by a ratio of the first and second code resistance, by disposing in series both the first code resistance corresponding to the pull-up code signal P_LEG_CD<0:4> and the second code resistance corresponding to the pull-down code signal N_LEG_CD<0:4> at its output node. The second termination resistance supply unit 60, which has the same configuration as the second resistance unit 34 shown in FIG. 3, supplies the pull-down resistance N_LEG_RSS in response to the pull-down code signal N_LEG_CD<0:4>.
The operation of the on-die termination circuit shown in FIGS. 1 to 3 will be described briefly.
First, the first resistance feedback unit 20, to which the pull-up code signal P_LEG_CD<0:4> and the input resistance ZQ are applied, outputs the feedback pull-up resistance P_LEG_FD. The ODT control unit 30 sequentially activates the control signals ODT_EN1P, ODT_EN2P, DT_UPP in response to the activation of the driving signal RES. Next, the first level detecting unit 42 outputs a pull-up detecting signal P_LEG_SN by amplifying a difference between the reference resistance RSS_REF and the feedback pull-up resistance P_LEG_FD in response to the control signal ODT_EN1P.
The first amplifier 44 outputs the pull-up level signal P_LEG_DT by amplifying the pull-up detecting signal P_LEG_SN in response to the control signal ODT_EN2P. The first register 50 stores the pull-up level signal P_LEG_DT and outputs the pull-up code signal P_LEG_CD<0:4> in response to the control signal DT_UPP.
Also, the ODT control unit 30 sequentially activates the control signals ODT_EN1N, ODT_EN2N and DT_UPN. The second resistance feedback unit 70 to which the pull-down code signal N_LEG_CD<0:4> and the pull-up code signal P_LEG_CD<0:4> are applied outputs the feedback pull-down resistance N_LEG_FD corresponding to the pull-down resistance N_LEG_RSS. The second level detecting unit 82 outputs the pull-down detecting signal N_LEG_SN by amplifying a difference between the reference resistance and the feedback pull-down resistance N_LEG_FD in response to the control signal ODT_EN1N.
Next, the second amplifier 84 outputs the pull-down level signal N_LEG_DT by amplifying the pull-down detecting signal N_LEG_SN in response to the control signal ODT_EN2N. The second register 90 stores the pull-down level signal N_LEG_DT and outputs the pull-down code signal N_LEG_CD<0:4> in response to the control signal DT_UPN.
The ODT control unit 30 repeatedly activates the control signals ODT_EN1P, ODT_EN2P, DT_UPP/ODT_EN1N, ODT_EN2N and DT_UPN in order that the above-mentioned processes are executed repeatedly for the predetermined number of times. Therefore, if the pull-up codes signal P_LEG_CD<0:4> and the pull-down codes signal N_LEG_CD<0:4> are set through the above-mentioned processing, the first and second termination resistance supply units 10 and 60 output the pull-up resistance P_LEG_RSS and the pull-down resistance N_LEG_RSS corresponding to the input resistance ZQ.
The conventional on-die termination circuit mentioned above produces both the pull-up codes signal P_LEG_CD<0:4> and the pull-down codes signal N_LEG_CD<0:4> of 5 bits and provides the pull-up resistance P_LEG_RSS and the pull-down resistance N_LEG_RSS through the codes signal. The pull-up codes signal P_LEG_CD<0:4> and the pull-down odes signal N_LEG_CD<0:4> is set in order that the pull-up resistance P_LEG_RSS and the pull-down resistance N_LEG_RSS respectively have a value of the input resistance ZQ.
The values of the pull-up and pull-down resistance are regulated by the activation of the corresponding code of the 5 bits of codes signal. That is, according to the number of bits of the code signal, the resolution of the pull-up and pull-down resistance is changed. For example, since an increase in the number of bits of the code signal means the number of transistors and resistors which are serially connected to them is increased, the fluctuation of the pull-up and pull-down resistance is reduced. On the contrary, if the number of bits of the code signal is decreased, the fluctuation of the pull-up and pull-down resistance is increased.
Accordingly, if the number of bits of the code signal is increased and the number of resistors and transistors controlled by the code signal is increased, it is possible to obtain the high resolution. However, there is a problem in that the size of a chip and layout is enlarged due to the increment of the resistors and the MOS transistors. Moreover, the burden on the size of a chip and layout can be reduced when the number of code signals is reduced; however, the resolution is decreased and a large error may occur in the pull-up and pull-down resistance as compared with the input resistance so that a malfunction is caused during high frequency operation.